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Coherency Verification Engineer

  • Remote
    • Barcelona, Catalunya [Cataluña], Spain
    • Bordeaux, Nouvelle-Aquitaine, France
    • Grenoble, Auvergne-Rhône-Alpes, France
    • Lille, Hauts-de-France, France
    • Lyon, Auvergne-Rhône-Alpes, France
    • Montpellier, Occitanie, France
    • Nantes, Pays-de-la-Loire, France
    • Paris, Île-de-France, France
    • Toulouse, Occitanie, France
    • Berlin, Berlin, Germany
    • Rome, Lazio, Italy
    • Atlanta, Georgia, United States
    • Austin, Texas, United States
    • Boca Raton, Florida, United States
    • Boston, Massachusetts, United States
    • Chicago, Illinois, United States
    • Columbus, Ohio, United States
    • Houston, Texas, United States
    • Florida City, Florida, United States
    • Dallas, Texas, United States
    • Detroit, Michigan, United States
    • Pondicherry, Tamil Nādu, India
    • Ahmedabad, Gujarāt, India
    • Delhi, Delhi, India
    • Fatorda, Goa, India
    • Hyderabad, Telangāna, India
    • Mumbai, Mahārāshtra, India
    • Indianapolis, Indiana, United States
    • Bangalore, Karnātaka, India
    • Aachen, Nordrhein-Westfalen, Germany
    • Neuruppin, Brandenburg, Germany
    • Emmen, Luzern, Switzerland
    • basel, Basel-Landschaft, Switzerland
    • Zürich, Zürich, Switzerland
    +33 more
  • Engineering

Job description

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Coherency Verification Engineer to join one of our clients' teams. If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you.

Responsibilities:

  • Verify complex digital designs at RTL level according to architecture and design specifications.

  • Develop and maintain verification environments using SystemVerilog and UVM.

  • Create, execute, and debug test plans for block-level, subsystem-level, and top-level verification.

  • Work on the verification of coherent systems, including cache-related functionality and interconnect behavior.

  • Validate designs involving CHI protocol, cache structures, coherency mechanisms, and system-level interactions.

  • Run and manage simulations, regressions, and debug failures using industry-standard verification tools.

  • Apply both formal and dynamic verification methodologies to identify design issues early.

  • Use scripting languages such as Python, Perl, Bash, or TCL to automate verification flows and regression processes.

  • Collaborate closely with architecture, design, and verification teams to analyze specifications, clarify requirements, and resolve issues.

  • Track, document, and communicate verification progress, bugs, coverage status, and technical risks.

  • Contribute to continuous improvement of verification methodology, tools, and best practices.

Job requirements

  • Master or PhD

  • English C1

  • Industrial experience +8 years

  • Proficiency in SystemVerilog and UVM

  • Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools 

  • Experience with simulation and simulation tools

  • Knowledge of revision control methodology and tools (git, svn)

  • Experience in block level and sub-system or top level verification

  • Experience with formal and dynamic verification

  • Strong problem-solving skills and attention to detail

  • Excellent communication and teamwork abilities

  • Knowledge of the CHI protocol

  • Understanding of caches' structure and parameters

  • Experience in verification of coherent systems

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